18.6 A 12b 75MS/s Pipelined ADC using Open-Loop Residue Amplification

Conventional pipelined ADCs use electronic feedback to achieve highly linear and drift insensitive transfer characteristics in their interstage gain elements. Especially in the converter frontend, amplifiers with large open-loop gain are needed to achieve the desired accuracy. Due to additional, conflicting low noise and high bandwidth requirements, precision amplifiers dominate the power dissipation in most high speed designs. We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple, power efficient open-loop stages. Our design achieves amplifier power savings of 62% (33mW) in the multi-bit first stage of a reference design [1] that was re-used and modified to evaluate the proposed concept.